1. Field of the Invention
The present invention pertains generally to memory circuits and, more particularly, to dynamic random access memory cells and a method for forming the same.
2. State of the Art
The microelectronics industry has been driven by the desire for increased device density and circuit miniaturization. One electronic circuit component where the desire for miniaturization is most evident is in the realm of data storage components. One such data storage component is computer memory and, more specifically, Random Access Memory (RAM). RAM cell densities have increased dramatically with each generation of new designs and have become one of the major driving sources for the formation of Integrated Circuit (IC) design. In order to accommodate continuing consumer demand for integrated circuits that perform the same or additional functions and yet have a reduced size as compared with available circuits, circuit designers continually search for ways to reduce the size of the memory cells which form memory arrays without sacrificing memory array performance.
With respect to memory ICs, the area required for each memory cell in a memory array contributes to the size of the memory array and the capacity (i.e., the amount of information that may be stored in each memory array) of the memory device. Therefore, the size and capacity of a memory device is a function of the dimensions of the memory cells. A conventional memory cell includes an information storage capacitor and an access transistor for selectively coupling the storage capacitor (and the charge stored therein) to other electronic circuitry (e.g., sensing, storing and refreshing circuitry). One way of increasing memory cell density is through the formation of a vertical memory cell wherein the storage capacitor and the access transistor are formed in a manner extending perpendicular from the general plane of the substrate. In order to form such structures, some of the interconnections and structures must be formed as tall narrow structures in close proximity with adjacent memory cells. The reduced size allows more computer chips to be fabricated on a semiconductor wafer and, assuming a similar functional chip yield, the cost per memory unit is reduced thereby providing a competitive advantage.
FIG. 1 illustrates a simplified cross-sectional view of a basic “stacked” configuration of a memory cell, in accordance with the conventional stacked capacitor technology utilizing a vertical transistor. Memory cells 10 and 30 are shown fowled on a substrate 12. Each of the memory cells 10 and 30 includes respective access transistors 14 and 34 and storage capacitors 16 and 36. During operation of, for example, memory cells 10 and 30, electrical charge representing information (e.g., a bit) is stored within storage capacitor 16 in conjunction with the activation of access transistor 14. In addition to the information passing through access transistor 14, the information is also bussed along a digitline illustrated in FIG. 1 as respective digitlines 18 and 38, electrically isolated by distance 32. The electrical isolation of each of the memory cells 10 and 30 from each other is essential to accurate conventional functionality but also contributes to the overall individual size of a memory cell and to the capacity of memory cells that may be fabricated in a manufacturable memory array.
As the minimum size for a photolithography feature “F” decreases, the aspect ratio of the stacked memory cell increases and the formation of features deep in the vertical dimension becomes problematic and affects the yield of functional devices. Therefore, it would be desirable to devise a memory cell and method for fabricating the same that includes structures and processes that are conducive to reduced dimensions and produce functional devices at those reduced dimensions.